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1 1 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 1 /32 ver 1.1 tft lcd specification model no.: td035 shec1 customer signature date free datasheet http:///
2 2 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 2 /32 table of contents no. item page cover sheet 1 table of contents 2 record of reversion 3 1 features 4 2 general specification 4 3 input / output terminals 5 4 absolute maximum ratings 8 5 electrical characteristics 9 6 block diagram 11 7 timing chart 12 8 power on/off sequence 16 9 optical characteristics 17 1 0 reliability 21 11 handling c autions 22 12 application note 23 1 3 mechanical drawing 31 1 4 packing drawing 32 free datasheet http:///
3 3 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 3 /32 record of reversion rev issued date description 1.0 aug, 15,2005 new 1.1 jam .25,2006 modify 1. feature s : cancel th e lcd m od ule i nclude s touch pane l free datasheet http:///
4 4 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 4 /32 1. feature s the 3.5 ? lcd module is the transflective active matrix color tft lcd module. ltps (low temperature poly silicon) tft technology is used and it ? s cog design. the lcd module includes backlight and tft lcd panel with minimal exter nal circuits and components required. 2. general specification item description unit display size (diagonal) 3. 5 inch (8.9cm) - display type trans flective - active area (hxv) 53.28 x 71.04 mm number of dots (hxv) 240 x rgb x 320 dot dot pitch (hxv) 0.074 x 0.222 mm color arrangement rgb stripe - color numbers 262,144 (6 bits) - outline dimension (hxvxt) 64.3 x 87.1x 2.95(max 3.15) * mm weight 35 g lcd panel + t - con + l/s 25 (typ) power consumption backlight 288 (typ, i f = 20ma) mw * exclude fpc and protrusions. free datasheet http:///
5 5 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 5 /32 3. input/output terminals 3.1 tft lcd module pin symbol i/o description remark 1 de i data enable signal 2 mclk i lcm pixel clock 3 reset i reset signal 4 yu - n/c 5 dvss i digital ground 6 vcom_i i vcom signal input for l cd panel 7 vcom_i i vcom signal input for lcd panel 8 avss i analog ground 9 vvee i input voltage for gate off 10 vvee i input voltage for gate off 11 vgh i input voltage for level shifter i/o 12 vgh i input voltage for level shifter i/o 13 d vss i digital ground 14 xl - n/c 15 vcom_h o positive power output for vcom connect big capacitor (10uf) 16 vcom_o o vcom signal of ic output 17 vcom_o o vcom signal of ic output 18 vcom_l o negative power output for vcom connect big capacitor (10 uf ) 19 avss i analog ground 20 dvdd i digital supply power 21 dvdd i digital supply powe r 22 avdd i analog supply power 23 avdd i analog supply power 24 yl - n/c 25 dvss i digital ground 26 iv6p o n/c 27 xr - n/c 28 tb_rl i shift direct ion (right/left) h: d1 ? d240 l: d240 ? d1 shift direction (top/bottom) h: top ? bottom l: bottom ? top 29 r5 i data bit input (red msb) 30 r4 i data bit input free datasheet http:///
6 6 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 6 /32 31 r3 i data bit input 32 r2 i data bit input 33 r1 i data bit input 34 r0 i data bit input (red lsb) 35 g5 i data bit input (green msb) 36 g4 i data bit input 37 g3 i data bit input 38 g2 i data bit input 39 g1 i data bit input 40 g0 i data bit input (green lsb) 41 b5 i data bit input (blue msb) 42 b4 i data bit input 43 b3 i data bit input 44 b2 i data bit input 45 b1 i data bit input 46 b0 i data bit input (blue lsb) 47 isc o n/c 48 scl i digital ground (serial interface clock input) 49 sda i digital ground (serial interface data input/output) 50 cs i digi tal ground (serial interface chip select input) 51 dvss i digital ground 52 hsync i horizontal sync input 53 dvss i digital ground 54 cm i display mode select cm=l: full display mode (65k/262k color) cm=h: partial display mode (8 color) 55 vs o positive power output for source driver 56 vsync i vertical sync input 57 led+ i led power (anode) 58 led+ i led power (anode) 59 led - o led power (cathode) free datasheet http:///
7 7 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 7 /32 60 led - o led power (cathode) 61 dvss i digital ground 3.2 ba ck light pin assignment (57,58) (59,60) free datasheet http:///
8 8 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 8 /32 4. absolute maximum ratings gnd =0v item symbol min max unit remark dvdd - 0.3 +3.6 v logic supply voltage avdd - 0.3 6 v vgh - 0 .3 + 19 v power supply for h/v driver vvee - 5.8 - 5.2 v note 1 backlight led forward voltage v f - 4 v backlight led reverse voltage v r - 5 v backlight led forward current (ta=25 j ) i f - 30 ma note2 operating temperature topr - 10 + 60 j storage temperature tstg - 20 + 70 j note1. the operating voltage is between +0.5 v and ? 5 .0v at the moment when the power is turned on note 2. relation between maximum led forward curre nt and ambient temperature is showed as bellow. free datasheet http:///
9 9 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 9 /32 5. electrical characteristics 5.1 driving tft lcd panel t a=25 j item symbol min typ max unit remark dvdd 2.4 2.8 3.3 v logic supply voltage avdd 4.8 5 5.6 v vgh 9.5 10 10.5 v power supply for h/v driver vvee - 5.8 - 5.5 - 5.2 v high vih 0.8dvdd ?e dvdd+0.3 logic input voltage low vil dvss ?e 0.2dvdd v r[5:0], g[5:0], b[5:0], clk de leakage current il - 1 ?e 1 ua dvdd supply curren t i dvdd - 0.74 1.9 ma note 1,2 avdd supply current i avdd - 1.65 4.0 ma note 3 vgh supply current i vgh - 0.07 0.2 m a vvee supply current i vvee - 0.05 0.5 m a note 1: the typical supply current specification is measured at the line inversion test patte rn (black and white interlacing horizontal lines as the diagram shown below) note 2: dvdd rush currents accept 120ma, 500u sec during system booting. note 3: gamma correction voltage is set to achieve the optimum at avdd =5.0v. use the voltage at level a s close to 5.0v as possible. 5.2 dc/dc spec input voltage item min typ max input current in put ripple (max) dvdd 2.4v 2.8v 3.3v 0.74 tbd avdd 4.8v 5v 5.6v 1.65 50 mv note 1 vgh 9.5v 10v 10.5v 0.07 150mv vvee - 5.8 v - 5.5 v - 5.2 v 0.05 tbd note 1: avdd is analog voltage supply therefore use as less ripple as possibl e. free datasheet http:///
10 10 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 10 /32 5.3 driving back light ta=25 j item symbol min typ max unit remark forward c urrent i f - 20 30 ma led/part led life time - - 10,000 - hr i f : 15ma forward current voltage v f - 3.6 4.0 v i f : 20ma ,led/part note: backlight driving circuit is recommend as the fix current circuit. free datasheet http:///
11 11 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 11 /32 6. block diagram vcom_o vcom_i TD035SHEC1 lcd module back light tft panel asic mclk,vsync,hsync de,reset,tb_rl,cm r [5:0],b [5:0],g [5:0] vvee led (+) led ?] - ?^ sda,cs,scl vcom_h vcom_l vs 10uf x5r 10v~16v dvdd vgh schottky diode recommended schottky diode vforward < 0.4v/100ma, vreverse > 15v v com circuit avdd free datasheet http:///
12 12 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 12 /32 7. timing chart 7.1 display timing ratings display mode parameter symbol conditions min typ max unit vertical cycle vp 323 326 340 line vertical data start vds vs+vbp 2 4 ?e line vertical front porch vfp 1 2 ?e line vertical blanking period vbl vs+vbp+vfp 3 6 ?e line vertical active area vdisp ?e 320 ?e line horizontal cycle hp 260 280 300 dot horizontal front porch hfp 4 10 ?e dot horizontal sync pulse width hs 8 10 ?e dot horizontal back porch hbp 18 20 ?e dot horizontal data start hds hs+hbp 26 30 ?e dot horizontal active area hdisp 240 240 240 dot 5.02 6.39 6.85 mhz normal clock frequency fclk tclk 199 156 146 ns free datasheet http:///
13 13 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 13 /32 input timing chart ?? vertical timing chart ?? vfp vp vdisp vbl vbp vfp vs vs hs de rgb[5:0] ?? horizontal timing chart ?? hfp hp hdisp hbl hbp hfp hs hs clk de rgb[5:0] * 1. the frequency of clk should be continued whether in display or blank region to ensure ic operating normally. * 1 free datasheet http:///
14 14 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 14 /32 setup/ hold timing ch art data clk tclk tckl tckh tds tdh tvsys tvsyh thsys thsyh thv vs hs phase difference of sync. maximum timing chart ?g minimum timing chart: free datasheet http:///
15 15 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 15 /32 7.2 ac characteristics : ratings parameter symbol conditions min typ max unit vertical sync. setup time tvsys 20 ?e ?e ns vertical sync. hold t ime tvsyh 20 ?e ?e ns horizontal sync. setup time thsys 20 ?e ?e ns horizontal sync. hold time thsyh 20 ?e ?e ns phase difference of sync. signal falling edge thv - (hs - 1) ?e 1hp - 1 clk clock ? l ? period tckl 30 50 70 % clock ? h ? period tckh 30 50 70 % d ata setup time tds 20 ?e ?e ns data hold time tdh 20 ?e ?e ns digital logic input trise/tfall 15 ns free datasheet http:///
16 16 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 16 /32 8. power on/off sequence power on sequence: dvdd & avdd & i nput signal reset vvee vgh power off sequence: vgh vvee dvdd & avdd & input signal reset (note 1) display start at the 10 th falling edge of vsync after reset rising (first 1 frame=white) (note 2) vgh will be pulled up to avdd - 0.7v before vg h power on , due to external schottky diode. (note 3) to avoid image retenti on ?a please input white image for two frame before power off . dvdd gnd avdd gnd gnd vvee vgh gnd reset gnd min: 1ms max: 5ms min: 0.1ms max: 10ms min: 1.1ms max: 10ms min: 1ms max: 5ms min: 0ms max: 2ms min: 0ms max: 1.5ms input signal gnd (note 1) (note 2) (note 3) free datasheet http:///
17 17 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 17 /32 9. optical characteristics 9.1 optical specification 9.1.1 back light off ta=25 j item symbol condition min typ max unit remarks k 11 + k 12 70 85 - viewing angles k 21 + k 22 cr = 2 75 95 - degree note 9 - 1 x 0.26 0.31 0.36 - ch romaticity white y k =0 0.29 0.34 0.39 - note 9 - 3 contrast ratio cr k =0 10:1 15:1 - - note 9 - 2 reflectivity r k =0 tbd 20 - % note 9 - 4 9.1.2 back light on ta=25 j item symbol condition min typ max unit remarks k 11 + k 12 100 120 - viewing angles k 21 + k 22 cr = 2 90 110 - degree note 9 - 1 response time tr +tf k =0 - 35 45 ms note 9 - 5 contrast ratio cr k =0 80:1 100:1 - - note 9 - 6 luminance l k =0 i f =20ma tbd 130 - cd/m 2 note 9 - 7 ntsc - - 32 36 - % note 9 - 7 uniformity - - 70 80 - % note 9 - 8 x 0.26 0.31 0.36 chromaticity white y k =0 0.28 0.33 0.38 - note 9 - 3 free datasheet http:///
18 18 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 18 /32 9.2 basic measure condition 9.2.1 driving voltage: vgh= 10.0v, vvee= - 5.5v 9.2.2 ambient temperature : ta=25 j 9.2.3 testing point: measure in the display center point and the test angle k =0 x 9.2.4 testing facility environmental illumination: = 1 lux a. system a b. system b fpc free datasheet http:///
19 19 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 19 /32 note 9 - 1: viewing angle diagrams ( measure system a) 3 o'clock x =0 x 9 o'clock x =180 x 6 o'clock x =270 x 12 o'clock x =90 x x k 11 k 12 k 21 k 22 normal k = 0 x k : viewing angle x : viewing direction note 9 - 2: contrast ratio in back light off (measure system a) contrast ratio is measured in optimum common electrode voltage. luminance with white image cr = luminance with black image note 9 - 3: white chromaticity as back light off : (measure system a) note 9 - 4: reflectivity (r ) (measure system a) in the measuring system a,. calculate the reflectance by the following formula . output from the white display panel reflectivity (r)= output from the reflectance standard x reflectanc e factor of reflectance standard free datasheet http:///
20 20 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 20 /32 note 9 - 5: definition of response time: (measure system b) 100% 90% 10% 0% luminance white white black tr tf note 9 - 6: contrast ratio in back light on (measure system b) contrast ration is measured in optimum common electrode voltage. luminance with white image cr = luminan ce with black image note 9 - 7: luminance: ( measure system b) test point: display center note 9 - 8: uniformity (measure system b) the luminance of 9 points as the black dot in the figure shown below are measured and the uniformity is defined as the formula: the minimum l uminance among 9 points uniformity = the maximum luminance among 9 points h 1/2h 1/6h 1/6h w 1/2w 1/6w 1/6w active area (w x h) free datasheet http:///
21 21 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 21 /32 10. reliability no test item condition 1 high temperature operation t a =+ 60 j , 2 40hrs 2 high temperature & high humidity operation ta=+40 j , 95% rh, 240hrs 3 low temperature operation ta= - 1 0 j , 240hrs 4 high temperature storage (non - operation) ta=+70 j , 240hrs 5 low temperature storage (non - operation) ta= - 2 0 j , 240hrs 6 thermal shock (non - operation) - 20 j ? 70 j , 3 0 cycles 30 min 30 min 7 surface discharge (non - operation) (lcd surface) c=150pf, r=330 [ ; discharge: air: 15kv; contact: 8kv 5 times / point; 5 points / panel 8 vibration (non - operation) frequency: 10~55hz; amplitude: 1.5mm sweep time: 11min test time: 2 hrs for each direction of x, y, z 9 shock (non - operation) acceleration: 100g; period : 6ms directions: x, y, z; cycles: three times free datasheet http:///
22 22 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 22 /32 11. handling c autions 11.1 esd (electrical static discharge) strategy esd will cause serious damage of the panel, esd strategy is very important i n handling. following items are the recommend ed esd strategy 11.1.1 in handling lcd panel, please wear gloves with non - charged material. using the conduction ring connects wrist to the earth and the conducting shoes to the earth necessary is. 11.1.2 the machine and work ing table for the panel should have esd protection strategy. 11.1.3 in handling the panel, ionized airflow decreases the charge in the environment is necessary. 11.1.4 in the process of assemble the module, shield case should connect to the ground. 11.2 environment wor king environment of the panel should be in the clean room. 11.3 others 11.3.1 turn off the power supply before connecting and disconnecting signal input cable. 11.3.2 because the connection area of fpc and panel is not so strong, do not handle panel only by fpc or bend fpc. 11.3.3 water drop on the surface or condensation as panel power on will corrode panel electrode. 11.3.4 as the packing bag open, watch out the environment of the panel storage. high temperature and high humidity environment is prohibited. 11.3.5 in the case the tft lcd module is broken, please watch out whether liquid crystal leaks out or not. if your hand touches liquid crystal, wash your hand s cleanly with water and soap as soon as possible free datasheet http:///
23 23 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 23 /32 12. application note 12.1 note for v - com circuit the circuit is designed for v - com fine - tune, please refer the circuit below to design application circuit. note: v ?g 5 v r2 ?g 10~30 k ohm r3 ?g 10~30 k ohm resistors tolerance ?g 0.5~1 % vcom waveform 0.1v 0.1v 4.34v 0.64v 4.44v 0.54v 2.49v v free datasheet http:///
24 24 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 24 /32 12.2 note for spi command the lcm support the 3 - pin s erial interface to set internal register. read/write bit rw, serial address a6 to a0 and serial data d7 to d0 are read at the rising edge of the serial clock, via the serial input pin. this data is synchronized on the rising edge of eighth serial clock and is then converted to parallel data. the serial interface signal timing chart is shown below. free datasheet http:///
25 25 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 25 /32 free datasheet http:///
26 26 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 26 /32 serial interface and reset parameter symbol conditions min. typ. max. unit clock cycle tcys - 150 - - ns clock high period tpwh - 60 - - ns clock low period tpwl - 60 - - ns data set - up time tdss - 60 - - ns data hold time tdhs - 60 - - ns cs high width tcsw - 1 - - us cs set - up time tcss - 60 - - ns cs hold time tchs - 70 - - ns scl to cs tscc 40 - - ns output access time tacc 10 - 50 ns output disable time tode 25 - 80 ns rstb low width trstbw - 1000 - - ns reset complete time tresc - - - 1000 ns free datasheet http:///
27 27 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 27 /32 command descriptions ?g reset the internal register by setting low level the resetb pin or software reset command. setting value register [dec] default [hex] bit name d7 d6 d5 d4 d3 d2 d1 d0 description remark chip id (read only) 0 0 0 i d 0(lds312a) 0 0 1 id 1(lds312b) - - - - 1 1 0 id 6 chipid[2:0] 1 1 1 id 7 the chip id can be changed by mask option. revision id (read only) 0 0 0 rev 0 0 0 1 rev 1 - - - - 1 0 1 rev 5(f) 1 1 0 rev 6 r0 00h revid[2:0] 1 1 1 rev 7 the revision id can be changed by mask op tion. vcom amplitude adjustment by vcomh voltage change 0 0 0 - 0.3v 0 0 1 - 0.2v 0 1 0 - 0.1v 0 1 1 0.0v 1 0 0 0.1v 1 0 1 0.2v 1 1 0 0.3v vcm8[7:5 ] 1 1 1 0.4v vcomh voltage change vcom voltage select 0 0 0 0 vcomh=3.90v ; vcoml=0.20v 0 0 0 1 vcomh=3.92v ; vcoml=0.22v 0 0 1 0 vcomh=3.94v ; vcoml=0.24v 0 0 1 1 vcomh=3.96v ; vcoml=0.26v 0 1 0 0 vcomh=3.98v ; vcoml=0.28v 0 1 0 1 vcomh=4.00v ; vcoml=0.30v 0 1 1 0 vcomh=4.02v ; vcoml=0.32v 0 1 1 1 vcomh=4.04v ; vcoml=0.34v 1 0 0 0 vcomh=4.06v ; vcoml=0.36v 1 0 0 1 vcomh=4.08v ; vcoml=0.38v 1 0 1 0 vcomh=4.10v ; vcoml=0.40v 1 0 1 1 vcomh=4.12v ; vcoml=0.42v 1 1 0 0 vcomh=4.14v ; vcoml=0.44 v 1 1 0 1 vcomh=4.16v ; vcoml=0.46v 1 1 1 0 vcomh=4.18v ; vcoml=0.48v r1 68h vcm8[3:0 ] 1 1 1 1 vcomh=4.20v ; vcoml=0.50v vcom_dc value setting interface mode select 0 vsync + hsync + de mode msel 1 vsync + hsync mode sync polarity select 0 negative syncp 1 positive input data mapping select 0 18 bit interface (262k color) dint 1 16 bit interface (65k color, r:g:b=5:6:5) input clock polarity change 0 no change r2 00h dckp 1 change mode slection vertical valid data start time select (vbp) 0 0 0 0 2 hsync 0 0 0 1 2 hsync 0 0 1 0 2 hsync 0 0 1 1 3 hsync 0 1 0 0 4 hsync 0 1 0 1 5 hsync - - - - - r3 04h vsts[3:0] 1 1 1 1 15 hsync default: qvga = 4 hsync qcif+ = 7 hsync 128x160 = 13 hsync 240x240 = 4 hsync free datasheet http:///
28 28 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 28 /32 setting value register [dec] default [hex] bit name d7 d6 d5 d4 d3 d2 d1 d0 description remark horizontal valid data start time select (hbp) 0 0 0 0 0 0 10 dck 0 0 0 0 0 1 10 dck 0 0 0 0 1 0 10 dck 0 0 0 0 1 1 10 dck 0 0 0 1 0 0 10 dck 0 0 0 1 0 1 10 dck 0 0 0 1 1 0 10 dck 0 0 0 1 1 1 10 dck 0 0 1 0 0 0 10 dck 0 0 1 0 0 1 10 dck 0 0 1 0 1 0 10 dck 0 0 1 0 1 1 11 dck 0 0 1 1 0 0 12 dck - - - - - - - 0 1 1 1 1 0 30 dck - - - - - - - r4 1dh hsts[5:0] 1 1 1 1 1 1 63 dck default: qvga = 30 dck qcif+ = 44 dck 128x160 = 36 dck 240 x 24 0 = 30 dck partial start line select 0 0 0 0 0 0 0 0 do not setting when pars[8]=0, gate256 is selected when pars[8]=1 0 0 0 0 0 0 0 1 gate1 is selected when pars[8]=0, gate257 is selected when pars[8]=1 0 0 0 0 0 0 1 0 gate2 is selected when pars[8]=0 , gate258 is selected when pars[8]=1 0 0 0 0 0 0 1 1 gate3 is selected when pars[8]=0, gate259 is selected when pars[8]=1 - - - - - - - - - 0 0 1 1 1 1 1 1 gate63 is selected when pars[8]=0, gate319 is selected when pars[8]=1 0 1 0 0 0 0 0 0 gate64 is selected when pars[8]=0, gate320 is selected when pars[8]=1 0 1 0 0 0 0 0 1 gate65 is selected when pars[8]=0, do not setting when pars[8]=1 0 1 0 0 0 0 1 0 gate66 is selected when pars[8]=0, do not setting when pars[8]=1 - - - - - - - - - 1 1 1 1 1 1 1 1 gate127 is selected when pars[8]=0, do not setting when pars[8]=1 1 0 0 0 0 0 0 0 gate128 is selected when pars[8]=0, do not setting when pars[8]=1 1 0 0 0 0 0 0 1 gate129 is selected when pars[8]=0, do not set ting when pars[8]=1 1 0 0 0 0 0 1 0 gate130 is selected when pars[8]=0, do not setting when pars[8]=1 - - - - - - - - - 1 1 1 1 1 1 0 0 gate252 is selected when pars[8]=0, do not setting when pars[8]=1 1 1 1 1 1 1 0 1 gate253 is selecte d when pars[8]=0, do not setting when pars[8]=1 1 1 1 1 1 1 1 0 gate254 is selected when pars[8]=0, do not setting when pars[8]=1 r5 01h pars[7:0] 1 1 1 1 1 1 1 1 gate255 is selected when pars[8]=0, do not setting when pars[8]=1 partial s tart line select 0 gate1 ? gate255 is selected r6 00h pars[8] 1 gate256 ? gate320 is selected when vsync+hsync+de mode, de=h: normal display line de=l: non - display line (white) when vsync+hsync mode, normal display line can be selected by r5,6,7 and 8. partial end line select 0 0 0 0 0 0 0 0 do not setting when pare[8]=0, gate256 is selected when pare[8]=1 0 0 0 0 0 0 0 1 gate1 is selected when pare[8]=0, gate257 is selected when pare[8]=1 0 0 0 0 0 0 1 0 gate2 is selected when pare[8]=0, gate258 is selected when pare[8]=1 0 0 0 0 0 0 1 1 gate3 is selected when pare[8]=0, gate259 is selected when pare[8]=1 - - - - - - - - 0 0 0 1 1 1 1 1 gate31 is selected when pare[8]=0, gate286 is s elected when pare[8]=1 0 0 1 0 0 0 0 0 gate32 is selected when pare[8]=0, gate287 is selected when pare[8]=1 0 0 1 0 0 0 0 1 gate33 is selected when pare[8]=0, gate288 is selected when pare[8]=1 0 0 1 0 0 0 1 0 gate34 is selected when pare[8 ]=0, gate289 is selected when pare[8]=1 - - - - - - - - - 1 0 1 1 1 1 1 0 gate63 is selected when pare[8]=0, do not setting when pare[8]=1 1 0 1 1 1 1 1 1 gate64 is selected when pare[8]=0, do not setting when pare[8]=1 1 1 0 0 0 0 0 0 gate65 is selected when pare[8]=0, do not setting when pare[8]=1 1 1 0 0 0 0 0 1 gate66 is selected when pare[8]=0, do not setting when pare[8]=1 - - - - - - - - - 1 1 1 1 1 1 0 0 gate252 is selected when pare[8]=0, do not setting when pare[ 8]=1 1 1 1 1 1 1 0 1 gate253 is selected when pare[8]=0, do not setting when pare[8]=1 1 1 1 1 1 1 1 0 gate254 is selected when pare[8]=0, do not setting when pare[8]=1 r7 20h pare[7:0] 1 1 1 1 1 1 1 1 gate255 is selected when pare[8]=0, do not setting when pare[8]=1 partial end line select 0 gate1 ? gate255 is selected r8 00h pare[8 ] 1 gate256 ? gate320 is selected when vsync+hsync+de mode, de=h: normal display line de=l: non - display line (white) when vsync +hsync mode, normal display line can be selected by r5,6,7 and 8. free datasheet http:///
29 29 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 29 /32 setting value register [dec] default [hex] bit name d7 d6 d5 d4 d3 d2 d1 d0 description remark software reset 0 normal r 10 00h cmdr 1 software reset vcom amplitude adjustment by vcomh voltage change 0 0 0 - 0.3v 0 0 1 - 0.2v 0 1 0 - 0.1v 0 1 1 0.0v 1 0 0 0.1v 1 0 1 0.2v 1 1 0 0.3v r11 67h vcm8[7:5 ] 1 1 1 0.4v vcomh voltage change (8 color partial mode) free datasheet http:///
30 30 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 30 /32 12.3 note for fpc circuit layout free datasheet http:///
31 31 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 31 /32 13. m echanical drawing free datasheet http:///
32 32 td035s hec1 the information contained herein is the exclusive property of toppoly optoelectronics corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of toppoly optoelectronics corporation. page: 32 /32 14. packing drawing desiccant tray with module total 15 layers empty tray(1 layer) rotation tray module with display face down *module quantity on 1 tray=8pcs cardboard carton module quantity in 1 carton=120pcs 2 1 4 5 ldpe bag 207 318 450 3 fix by adhesion tape td035s hec1 module delivery packing method 14.1 module packed into tray cavity with display face down. 14.2 tray stacking with 15 layers and with 1 empty tray above the stacking tray unit. 2 pcs desiccant put abov e the empty tray. 14.3 stacking tray unit put into the ldpe bag and fix by adhesive tape. 14.4 put 1pc cardboard inside the carton bottom, then pack the finished package into the carton. 14.5 carton sealing with adhesive tape. free datasheet http:///

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